Read/write memory integrated circuits store data by a process called writing and permit the subsequent retrieval of that data by a process called reading. In a conventional memory circuit, data is stored in a plurality of storage locations arranged as an array of memory cells. Each storage location is identified by an address, which might include both a row identifier and a column identifier. The amount of data that can be stored in the cells of a memory integrated circuit is known as the storage capacity of the circuit. In conventional memory circuits, internal data lines transfer the data to the storage locations during a write cycle and transfer the data from the storage locations during a read cycle.
One specific type of memory circuit is known as a random access memory circuit ("RAM"). Random access memory circuits permit the storage locations to be accessed randomly, and further permit data to be both read from and written to the storage locations of the memory circuit. RAM circuits generally come in two forms. The first form of RAM is known as a static RAM circuit ("SRAM"). A primary characteristic of an SRAM circuit is that the circuit uses latches so that the storage locations of the circuit indefinitely retain the data stored therein, provided power is connected to the circuit. The second form of RAM is known as a dynamic RAM circuit ("DRAM"). A primary characteristic of a DRAM circuit is that the circuit uses charge storing elements, such as capacitors, to retain the stored data in the storage locations, and the circuit must periodically recharge (i.e., refresh) the data in order to retain same.
As will be appreciated by those skilled in the art, prior art memory integrated circuits that require a large number of internal data lines typically have high power requirements, have relatively slow speed, and have generally high power and ground line resistance. This high resistance generates undesirable power supply and ground noise, which limits the speed of the circuits.
Although the present invention shall be shown and described in the form of an embedded DRAM macro, those skilled in the art will appreciate that the principles of the present invention are applicable to memory integrated circuits generally, and more particularly to high speed memory integrated circuits requiring a large number of internal data lines.
Throughout this specification, reference will often be made to inputs, outputs, lines and busses, among other things, that are included within the preferred form of the memory integrated circuit. Throughout this specification, if reference is made to one of these, such as a data line, and that data line is given a particular reference numeral for identification purposes, then another data line given the same reference numeral but with a "B" designation shall be understood to be its complement. For instance, a data line 300B would be understood to be the complement of data line 300. Conversely, data line 300 would be the complement of data line 300B. Generally speaking, if they are not tied together (such as when they are equalized), or if they are not driven to the same logic state for a special purpose, when data line 300 is HIGH, data line 300B is LOW. Conversely, absent special conditions, when data line 300 is LOW, data line 300B is HIGH. Those skilled in the art will appreciate this concept and understand this designation hereby incorporated herein by reference.
FIG. 1 illustrates the architecture for a conventional DRAM memory macro. In particular, FIG. 1 shows an embedded DRAM macro 20A having a first laterally extending boundary 22 and an associated laterally extending boundary 24 defining an opposite side thereof. Macro 20A further includes two opposing longitudinally extending boundaries 26, 28. DRAM macro 20A includes a plurality of memory cell arrays or banks 30, each of which includes a plurality of memory cells (i.e., storage locations). Each memory cell has a unique row and column address for identification purposes.
Column decoder logic circuitry 32 is positioned along the length of, and in close proximity to, boundary 26. As shown, several column select lines 34 extend laterally from column decoder 32 across macro 20A and over memory cell banks 30.
Longitudinally extending bands 36 separate adjacent memory cell banks 30. Bands 36 each include a plurality of sense amplifiers (not shown). For this reason, bands 36 are generally referred to as sense amp bands by those skilled in the art. As shown in FIG. 1, in conventional DRAM macros, data lines 38, power lines 40 and ground lines 42 extend longitudinally across macro 20A through sense amp bands 36. Power lines 40 are generally set at a voltage referred to as Vcc by those skilled in the art, and ground lines 42 are generally set at a voltage referred to as Vss by those skilled in the art.
As just described, in this conventional architecture, the data lines 44 and the power and ground lines 40, 42 run through the sense amp bands 36. Further, the column select lines 34 typically run across the memory arrays 30 in a direction generally transverse to the data lines. Although suitable for a variety of applications, this conventional architecture for macro 20A is not suited for memory circuits having a large number of internal data lines 38. In particular, only a small number of data lines, perhaps only two to four data lines, can run through each sense amp band 36. This limitation is due to chip area considerations and the consequential limited width of the sense amp bands 36. In addition, with respect to this conventional architecture, the power and ground lines 40, 42 have a relatively high resistance. Notably, because they run through the sense amp bands, the power and ground lines must be relatively narrow, which, in turn, causes them to have a relatively high resistance.
FIG. 2 illustrates a DRAM macro architecture that would accommodate a relatively large number of internal data lines. The DRAM macro architecture shown in FIG. 2 would include global data lines 44 extending laterally across macro 20B and over the memory arrays 30, in a direction generally transverse to the sense amp bands 36, which extend longitudinally across the macro. Macro 20B would further include local data lines 46 that extend longitudinally through the sense amp bands 36 and connect with the global data lines 44. Each of these local data lines 46 would be shared by a predetermined set of the sense amplifiers contained within sense amp bands 36. Each local data line 46 would be associated with exactly one set of sense amplifiers. Further, each set of sense amplifiers would be associated with exactly only one local data line 46.
During a read operation, a selected one of the sense amplifiers in one of the sets of sense amplifiers would be enabled by a signal present on its associated column select line 34. Thereafter, the data stored in the memory cell associated with that selected sense amplifier would be transferred to the local data line 46 connected to that selected sense amplifier. The data then, in turn, would be transferred to a global data line 44 connected to that local data line 46 for subsequent processing by circuit elements positioned external to macro 20B.
During a write operation, data would be sent from an external circuit element (e.g., microprocessor) to the memory macro 20B for storage at an address therein. The data first would be transferred from a global data line 44 to a local data line 46 connected thereto. A selected one of the sense amplifiers in one of the sets of sense amplifiers would be enabled by a signal present on its associated column select line 34. Thereafter, the data present on the local data line 46 connected to the selected sense amplifier would be transferred to the memory cell associated with that selected sense amplifier for storage in the memory array 30 at that storage location.
Although the architecture shown in FIG. 2 would allow for a large number of internal data lines without requiring any area penalty, it would have two notable disadvantages. First, the capacitance of the global data lines 46 would be relatively high, which would decrease performance and increase power consumption. Second, because they would run through the sense amp bands 36, which have a limited width, the power and ground lines 40, 42 would be relatively narrow. As explained above, this would cause them to have undesirably high resistance.
Referring now to another architecture shown in FIG. 3, a macro 20C shown therein would include: column select lines 34 extending laterally across the macro and over the memory arrays 30, global data lines 44 extending in that same direction, local data lines 46 extending longitudinally through the sense amp bands 36, and a plurality of power and ground lines 40, 42. Some of the power and ground lines 40, 42 would extend laterally across the array, while others would extend longitudinally through the sense amp bands 36. Those power and ground lines 40, 42 that would extend laterally across macro 20C could be of larger width than those described above. Furthermore, in this architecture, those power and ground lines 40, 42 that would extend longitudinally through the sense amp bands 36 would increase the effective width of the power and ground bussing. Accordingly, the power and ground bussing that would be utilized in this architecture would have reduced resistance, thereby reducing power consumption and ground noise.
Nevertheless, the architecture for macro 20C shown in FIG. 3 would not be optimal for high speed memory integrated circuits requiring a large number of internal data lines. In particular, because its column select lines 34, global data lines 44, and power and ground lines 40, 42 would extend laterally across macro 20C, space considerations would limit the ability to fit the macro in a small chip. As a practical matter, it would be necessary to add additional layers of metal to accommodate all of the laterally extending lines of this architecture. This addition of metal layers would add to the manufacturing cost of the memory circuit and would also increase the capacitance of the column select lines 34 and the global data lines 44, which would decrease performance and increase power consumption.
FIGS. 15A and 15B illustrate a conventional layout for generally parallel signal conductors in integrated circuits. In this depicted conventional layout, a plurality of generally parallel signal conductors designated 60 extend in generally the same direction. There are ten conductors shown in FIGS. 15A and 15B. Conductors 60 are all included within the same level. This depicted layout is useful for certain, limited purposes. However, this layout results in an inefficient use of chip space, particularly when a high number of conductors 60 are present in a particular circuit design. In the memory circuit disclosed herein, conductors 60 could represent the read and/or write data lines. As will be appreciated, when a relatively high number of internal data lines are used, the layout depicted in FIGS. 15A and 15B is inefficient.
FIGS. 16A and 16B illustrate another conventional layout for generally parallel signal conductors in integrated circuits. In this depicted conventional layout, a first set of generally parallel signal conductors 62 is included within a first level designated A and a second set of generally parallel signal conductors 64 is included within a second level designated B. As shown, the conductors 62, 64 are interleaved on different levels. As will be appreciated by those skilled in the art, the layout illustrated in FIGS. 16A and 16B is much more efficient than the layout illustrated in FIGS. 15A and 15B. Nevertheless, because the conductors 62 of the first set on level A are coincident and vertically overlapping the conductors 64 of the second set on level B, a vertical capacitance comprising both a vertical parallel plate capacitance and a vertical fringe capacitance exists on the conductors, which translates into slower signal propagation speed. The utilization of adjacent levels also contributes to the vertical capacitance to reduce performance.
In light of the foregoing, it will be appreciated by those skilled in the art that the architecture generally used with conventional memory circuits is unsuitable for a memory circuit exhibiting reduced power and ground bussing resistance, and reduced data line capacitance. It will also be understood that that architecture is unsuitable for a memory circuit requiring a large number of internal data lines. Furthermore, it will be appreciated by those skilled in the art that many of the possible architectures for such memory circuits, although suitable for limited applications, would have considerable drawbacks that would limit their use in electronic devices. Some of these drawbacks include lesser performance (slower speed), high power consumption and increased manufacturing cost.
One object of an illustrated embodiment is that it provides for a high speed memory circuit having a relatively large number of internal data lines.
Another object of an illustrated embodiment is that it provides for relatively low capacitance on its internal data lines, which permits faster data transfer speed and requires less power.
Still another object of an illustrated embodiment is that it has relatively low resistance power and ground bussing.
Yet another object of an illustrated embodiment is that it has separate read and write data path circuits.
Another object of an illustrated embodiment is that it provides for an integrated circuit design having reduced capacitance.
These and other objects of the illustrated embodiments will become apparent from the following description. It will be understood, however, that an apparatus could still appropriate the invention claimed herein without accomplishing each and every one of these objects, including those gleaned from the following description. The appended claims, not the objects, define the subject matter of this invention. Any and all objects are derived from the illustrated embodiments, not necessarily the invention in general.